I’m working hard on a research project, hoping to finish it up in the next week or so. As a PhD student, my life revolves around conference paper deadlines. Sadly, these deadlines are not extendable.
I’m designing a computer chip (or at least part of one). It’s a bit tricky because this chip is very complex. Although the ideas behind the tricky logic aren’t new or convoluted, there’s a lot of transistors involved. All of these transistors really tax every step of the design process and things that should work now result in thousands of oddly worded error messages.
The first step of my hardware design process is to write code in Verilog. Verilog is best described as the bastard child of a simple programming language like C and an evil flowchart. Although it seems like any other program, the code is more concerned about generating output bits from input bits. There’s a lot of timing involved and you have to think about how inputs will change over time. I use a design style called “Two-phase clocking”, which is a nice way of saying that some inputs are gibberish some of the time, and the other inputs are gibberish during other times.
It took me about three weeks to really finish the Verilog code and test it out. There’s a lot of work beyond this, converting the code to a chip blueprint, so it’s important that the Verilog works. You don’t want to do any of this work twice.
After this, I put my Verilog code through a program called “Design Compiler”. This takes my code and converts it into a giant computer chip recipe. It doesn’t design the chip, but decides what transistors to use and how they should connect up. Usually this process takes 15-20min, but it’s been taking me about 12 hours. That’s after a lot of fiddling with the program.
Design Compiler will spit out this recipe as another Verilog file. However, this file is much more detailed and really big. The idea is that this Verilog file is an optimized way to implement the high level ideas from my original Verilog file. Sometimes I get a lot of weird timing warnings about arcs and whatnot. This is not comforting.
The next program I have to use is Encounter. This takes the new Verilog file and comes up with a blueprint, figuring out where each of the transistors should go. This has about 10 steps and half of the time they fail for some unknown reason. One of these steps takes 60+ minutes, so it’s always fun when you go through that and find out the program has given up. When it does work, you get a spiffy looking chip, like in the Intel ads. Mine looks like this:
After all of that is done, I take the blueprint and put it in a program called Cadence. Although Cadence does a lot more, I’m only using it to make sure my blueprint makes sense and acts like it should. I’m also currently trying to analyze it to understand how all of the transistors interact. The first two steps (making sure it will work in reality) took a few hours. The analysis step, called PEX for reasons too boring to put here, took about 5 hours and abruptly failed without reason an hour ago. I changed a few settings and it’s off again. I’ll be waking up at 3am to see how that went.
After that step (please, please let PEX work this time), I’ll run the analysis through HSIM. HSIM tries to simulate the timing and energy of my circuit from the PEX analysis. This will likely take a long time as well. If that step works, I’ll have all of the data I need to write my paper.
